For economies of scale, integrated circuits (or die) are fabricated in a batch on a semiconductor wafer. The upper limit on wafer diameter continues to go up. Presently, the state of the art in wafer diameter is 200 millimeters, or around eight inches, with experimental wafers in the 300 millimeter, or twelve inch, range.
Semiconductor equipment manufactures often tailor equipment to a particular wafer diameter or range of wafer diameters. As wafer diameters increase, the equipment built to process the smaller diameter wafers becomes obsolete. Typically, this does not cause a problem since the die on the larger diameter wafers is the only device that is processed and a change in the wafer diameter may require an upgrade of all of the equipment needed to process the larger wafer. However, this does cause a problem for those who manufacturer multi-chip modules (MCMs).
An MCM is a type of package that contains more than one integrated circuit. MCM manufacturers often receive the integrated circuits to be built into an MCM in wafer form. An MCM module may contain the latest microprocessor which may be fabricated in the most expensive state-of-the-art process (i.e., largest diameter wafer process) as well as single transistors which may be fabricated in the most economical fabrication process (i.e., a smaller wafer diameter process that is a couple of generations older than the state-of-the-art). So, MCM manufacturers must often handle wafers of different diameters. It would be prohibitively expensive for an MCM manufacturer to operate and maintain multiple sets of equipment to handle different diameter wafers.
MCM manufactures are always looking for ways to reduce the size of the integrated circuits that are contained within an MCM. reducing the size of the integrated circuits may reduce the size of the MCM. having an MCM that fits into a place that it did not fit in before may create a new market. Furthermore, reducing the size of the integrated circuits that go into the MCM may create space in an MCM of a particular size where other integrated circuits may be placed. Adding integrated circuits to an MCM may increase performance or functionality.
One of the ways that MCM manufacturers reduce the size of the integrated circuits contained in an MCM is to thin the integrated circuits. Since the integrated circuits may be received in wafer form and the wafers may come in different diameters, it would be more economical for an MCM manufacturer if it were able to thin semiconductor wafers of different diameters on the equipment that it presently has for thinning wafers. Since wafers of the same diameter are already properly sized for the thinning equipment, and wafers of larger diameter may be reduced in diameter to be of proper size, the present invention is a method of thinning wafers of diameters that are smaller than the thinning equipment was designed to thin.
U.S. patent application Ser. No. 08/900,869, filed Jul. 25, 1997, entitled "METHOD OF THINNING INTEGRATED CIRCUITS RECEIVED IN DIE FORM," discloses a method of placing individual die with an opening cut in a wafer to form a pseudo-wafer so that individual die or any type may be thinned. The present invention uses a wafer with an opening cut therein in its method of thinning a wafer of a smaller diameter than the thinning equipment was designed to thin.
U.S. Pat. No. 5,256,599, entitled "SEMICONDUCTOR WAFER WAX MOUNTING AND THINNING PROCESS," discloses a method of thinning an entire wafer. U.S. Pat. No. 5,256,599 does not disclose a method of thinning a wafer of a smaller diameter than the thinning equipment was designed to thin as does the present invention. U.S. Pat. No. 5,256,599 is hereby incorporated by reference into the specification of the present invention.
U.S. Pat. No. 5,273,940, entitled "MULTIPLE CHIP PACKAGE WITH THINNED SEMICONDUCTOR CHIPS," discloses a method of electrically connecting standard thickness dice in a multi-chip-module, encapsulating the dice, and thinning the encapsulant and the dice. U.S. Pat. No. 5,273,940 does not disclose a method of thinning a wafer of a smaller diameter than the thinning equipment was designed to thin as does the present invention. U.S. Pat. No. 5,273,940 is hereby incorporated by reference into the specification of the present invention.
U.S. Pat. No. 5,324,687, entitled "METHOD FOR THINNING OF INTEGRATED CIRCUIT CHIPS FOR LIGHTWEIGHT PACKAGED ELECTRONIC SYSTEMS," discloses a method of placing standard thickness dice circuit-side up in various wells in a semiconductor wafer. U.S. Pat. No. 5,324,687 does not disclose a method of thinning a wafer of a smaller diameter than the thinning equipment was designed to thin as does the present invention. U.S. Pat. No. 5,324,687 is hereby incorporated by reference into the specification of the present invention.